1. Field of the Invention
The present invention relates to a data transfer control system for a data processing system which directly controls data transfer between a memory and peripheral functional circuits without the use of a central processing unit.
2. Description of the Prior Art
FIG. 4 is a block diagram of the configuration of a data processing system which employs a conventional data transfer control system. In the figure, reference numeral 2 represents a central processing unit (CPU) for performing arithmetic and control operations for data processing, 3 a memory for storing data (programs and other data) required for data processing, 4 peripheral functional circuits having special functions for data processing, 1 a DMA transfer circuit as a direct transfer circuit for directly transferring data from a source peripheral functional circuit 4 or memory 3 to a destination memory 3 or peripheral functional circuit 4 through a data bus 8 by acquiring the right to use the data bus 8 and bypassing the CPU 2, and 9 an address bus for specifying an address of such a device as the memory 3. The above-mentioned DMA transfer circuit 1 comprises a DMA transfer request accept circuit 5, a DMA transfer data buffer 6 and a DMA transfer control circuit 7. In FIG. 4, reference letter A represents the data input/output line of the CPU2, B the address output line of the CPU 2, C the data input/output line of the DMA transfer circuit 1, D the address output line of the DMA transfer circuit 1, E the data input/output line of the memory 3, and F the address input line of the memory 3. Letter G represents a DMA request signal line from the peripheral functional circuits 4, H a DMA transfer trigger signal line from the DMA transfer request accept circuit 5 to the DMA transfer control circuit 7, I a CPU stop request signal line from the DMA transfer control circuit 7 to the CPU 2, J a CPU stop complete signal line from the CPU 2 to the DMA transfer control circuit 7, K a DMA transfer complete signal line from the DMA transfer control circuit 7 to the CPU 2, and L a data transfer control line from the DMA transfer control circuit 7 to the DMA transfer data buffer 6.
FIG. 5 is a block diagram of the configuration of a conventional DMA transfer circuit. In the figure, components corresponding to those shown in FIG. 4 are denoted at like reference symbols, and their description will be omitted. In the figure, reference numeral 10 represents a bus use right decision circuit, 11 a bus access control circuit, 12 a transfer pointer, 13 a transfer counter, 14 a source address pointer, and 15 a destination address pointer. Reference letter D' represents the address output line of the source address pointer 14, D" the address output line of the destination address pointer 15, M a DMA transfer start signal line, N a DMA transfer complete signal line to the bus use right decision circuit 10, O a read trigger signal line to the DMA transfer data buffer 6, O' a write trigger signal line to the DMA transfer data buffer 6, P a count signal line to the transfer counter 13, Q a transfer data complete signal line from the transfer counter 13, R a count value of the transfer pointer 12, S a source address output request signal line, and T a destination address output request signal line.
The operation of the data processing system will be described hereafter with reference to FIG. 4. When a DMA transfer request signal is inputted from the peripheral functional circuits 4 to the DMA transfer request accept circuit 5 through the signal line G, the DMA transfer request accept circuit 5 outputs a DMA trigger signal to the DMA transfer control circuit 7 through the signal line H. The DMA transfer control circuit 7 which has accepted the DMA trigger signal outputs a CPU stop request signal to the CPU 2 through the signal line I to stop the operation of the CPU 2. The CPU 2 which has accepted the CPU stop request signal stops operation and outputs a CPU stop complete signal to the DMA transfer control circuit 7 through the signal line J. Through these operations, the data bus use right is transferred from the CPU 2 to the DMA transfer circuit 1.
The DMA transfer circuit 1 which has acquired the data bus use right outputs a source address to the address bus 9 through the signal line D for input into the memory 3 through the signal line F. The memory 3 which has received the source address outputs transfer data from the source address thereof to the data bus 8 through the signal line E. The transfer data outputted to the data bus 8 is inputted into the DMA transfer data buffer 6 through the signal line C. After the transfer data is inputted into the DMA transfer data buffer 6, a destination address is outputted to the address bus through the signal line D, and the transfer data is written through the signal line C, the data bus 8 and the signal line E to the destination address of the memory 3 which has received the destination address through the signal line F. These operations are repeated until data transfer is completed.
When DMA transfer is completed, the data bus use right is transferred from the DMA transfer circuit 1 to the CPU 2, and the DMA transfer control circuit 7 outputs a DMA transfer complete signal to the CPU 2 through the signal line K, whereby the CPU resumes operation.
Next, the operation of the DMA transfer control circuit 7 will be described in conjunction with FIG. 4 and FIG. 5. When the CPU stop signal is inputted into the bus use right decision circuit 10 through the signal line J, the bus use right decision circuit 10 transfers the bus use right from the CPU 2 to the DMA transfer circuit 1, and outputs a DMA transfer start signal to the bus access control circuit 11 through the signal line M. The bus access control circuit 11 which has received the DMA transfer start signal outputs a source address output request signal to the source address pointer 14 through the signal line S. The source address pointer 14 which has received the source address output request signal outputs a source address to the address bus 9 through the signal line D'. At the same time, the bus access control circuit 11 outputs a read trigger signal to the DMA transfer data buffer 6 through the signal line O so as to read out the transfer data outputted from the source address to the DMA transfer data buffer 6 from the data bus 8 through the signal line C.
When the reading of the transfer data from the source address is completed, the bus access control circuit 11 outputs a destination address output request signal to the destination address pointer 15 through the signal line T. The destination address pointer 15 which has received the destination address output request signal outputs a destination address to the address bus 9 through the signal line D". At the same time, the bus access control circuit 11 outputs a write trigger signal to the DMA transfer data buffer 6 through the output line O' so as to write the transfer data at the destination address.
When the transfer of one-byte data is completed with the above-mentioned operation, the bus access control circuit 11 outputs a count signal to the transfer counter 13 through the signal line P. The transfer counter 13 counts down the value of the transfer pointer 12 through the signal line R. If the value of the transfer pointer 12 is not "0" after countdown, the bus access control circuit 11 performs the next DMA transfer.
The transfer counter 13 outputs a transfer data complete signal to the bus access control circuit 11 through the signal line Q when the value of the transfer pointer 12 becomes "0". The bus access control circuit 11 which has received the signal completes DMA transfer, and outputs a DMA transfer complete signal to the bus use right decision circuit 10 through the signal line N. The bus use right decision circuit 10 transfers the bus use right from the DMA transfer circuit 1 to the CPU 2, and thereafter outputs a DMA transfer complete signal to the CPU 2 through the output line K, whereby the CPU 2 resumes operation.
As described above, according to the conventional data transfer control system, the bus use right is transferred from the CPU to the DMA transfer circuit for DMA transfer after the suspension of the CPU, and the bus use right is transferred from the DMA transfer circuit to the CPU for the resumption of the CPU after the completion of DMA transfer.
Since the conventional data transfer control system is such as described above, the priority order of the bus use right (the DMA transfer circuit has priority over the CPU) is fixed irrespective of the operation state of the CPU or the number of data pieces to be transferred. Therefore, during DMA transfer, the CPU cannot be used for processing, which causes the problem of total processing efficiency of the data processing system being lowered.